This invention relates to a semiconductor device which has a level conversion circuit that converts different levels of logical signals, and particularly to a semiconductor device with an ECL/TTL level conversion circuit that converts ECL level logical signals into TTL level logical circuits.
Generally, digital circuit elements have so-called Standard Logic for general purpose use and are classified into ECL systems, TTL systems, CMOS systems, etc. These standard logic units are widely used. For example, ECL system units are used for high speed operation components of CPUs and the like because of their superior signal transmission characteristics, while TTL system units are used for failure-free logical circuits because of their high noise tolerance.
These standard logic units have logic levels peculiar to their systems. For instance, the ECL system has a logic level between the -4.5 V (or 5.2 V) constant power source V.sub.EE on the negative side and the constant power source GND on the ground side, whereas the TTL system has a logic level between the +5 V constant power source V.sub.CC on the positive side and constant power source GND on the ground side. Therefore, signal transmission between different standard logic units requires logic level conversion. Level conversion circuits are therefore used for, i.e. standardization or matching of logic levels between different standard logic units. Especially, recently, it has been required that semiconductor devices attain a higher degree of speed and integration due to the development of devices (e.g. computer systems) loaded therewith. Consequently, semiconductors device s tend to consume more electricity, but it is desirable to minimize the consumed current of the devices loaded with semiconductor devices. Therefore, it is necessary to minimize the consumed current of these semiconductor devices as much as possible.
FIG. 1 is an example of conventional ECL/TTL level conversion circuit. In FIG. 1, 1 is a level conversion circuit using a negative voltage power source. The level conversion circuit 1 is configured with a P channel MOS transistor P1 to which gate ECL level input signal IN is input with P1's drain connected with the gate of N channel MOS transistor N2 through output terminal OUT; a N channel MOS transistor N1, connected serially with P1, whose gate is connected with the drain of a P channel MOS transistor P2 through output terminal OUT; a P channel MOS transistor P2 to which gate the complement signal IN of the ECL level input signal IN is input with P2's drain connected with N1's gate through an output terminal OUT, and a N channel MOS transistor N2, connected serially with F2, whose gate is connected with P1's drain through output terminal OUT. In FIG. 1, IN is an ECL level input signal with IN being its complement signal, and OUT is TTL level output signal with OUT being its complement signal. V.sub.CC refers to a positive voltage power source (GND), and V.sub.EE refers to a negative voltage power source.
In this configuration, if "L" level and "H" level are input respectively to inputs IN and IN, then P1 and N2 become ON and P2 and N1 become OFF. Therefore, the flip-flop configured by P1, P2, N1 and N2 is in a stable condition, and output OUT becomes approximately OV. Meanwhile, if "H" level and "L" level are input respectively to inputs IN and IN, then P2 and N1 become ON and P1 and N2 become OFF. Therefore, the flip-flop configured by P1, P2, N1 and N2 is in a stable condition, and output OUT becomes V.sub.EE (approximately --5.2 V). These operations convert ECL level signals into TTL level signals.
However, these existing semiconductors have had a problem in that they have failed to reduce the current consumed due to a through current at switching for the reason stated below.
At first, if "L" level and "H" level are input respectively to inputs IN and IN, transistors P1 and N2 are ON and transistors P2 and N1 are OFF. Next, when the input phase is reversed, the transistors' switching sequence will be performed in such a manner that only after P channel transistors P1 and P2 become OFF and ON respectively, N channel transistors N1 and N2 become ON and OFF respectively. Consequently, both P2 and N2 are ON, when the phase is reversed, and a through current, irrelevant to switching, flows from the positive voltage power source V.sub.CC to the negative voltage power source V.sub.EE. Since the current consumed is the sum of the current required for switching and the through current which is irrelevant to switching, the through current that requires an increase in current consumption is not desirable.